1. Field of the Invention
The present invention relates to dynamic random access memory cell structures and fabrication methods therefor, and more particularly to a vertical trench transistor and trench capacitor structure and fabrication process therefor.
2. Background Art
The following references are representative of the background art available prior to the present invention.
Japanese Patent No. 59-19366 describes a vertical FET semiconductor memory device disposed between condensers for storing charge. Electrostatic capacity from the device substrate is utilized for storing the memory charge.
Japanese Patent No. 58-3269 relates to a vertical one-transistor MOS memory cell having a cylindrical gate electrode, an insulating layer and source and drain layers. The source or drain layer can also be one electrode of a charge storage capacitor.
The publication entitled DYNAMIC RAM CELL STRUCTURE, IBM Technical Disclosure Bulletin, Vol 27, No. 12, May 1985 at page 7051 relates generally to integrated circuit structures and more particularly to dynamic random-access memory (DRAM) cell construction having a stacked planar MOS access transistor over a buried pn junction storage capacitor.
The publication entitled HIGH DENSITY VERTICAL DRAM CELL, IBM Technical Disclosure Bulletin, Vol. 29, No. 5, October 1986 at page 2335, describes a high density vertical trench DRAM (dynamic random-access memory) cell wherein the transfer device is oriented in the vertical direction and is positioned over a trench storage capacitor. A shallow trench filled with polysilicon or polycide serves as the MOS transfer device gate. Transfer MOSFETs of adjacent cells share the same gate.
The publication entitled DYNAMIC RAM CELL WITH MERGED DRAIN AND STORAGE, IBM Technical Disclosure Bulletin, Vol. 27, No. 11, April 1985 at page 6694 relates generally to the fabrication of integrated circuits and more particularly to the construction of a dynamic random-access memory cell requiring less space.